Is it possible in GNU / Make to set one rule for different purposes?

For example, I have two goals (1 executable file): targ0.axf and targ1.axf . Both depend on the same object files, both are built the same way:

 targ0.axf: file0.o file1.o $(LD) $^ -o $@ $(LFLAGS) targ1.axf: file0.o file1.o $(LD) $^ -o $@ $(LFLAGS)

Is it possible to write something shorter?

    1 answer 1

    yes you can. for example:

     targ0.axf targ1.axf: file0.o file1.o $(LD) $^ -o $@ $(LFLAGS)
    • Only you need to remember to specify both goals, for example at all: for a complete build - avp
    • @avp, this is a valuable comment, although it has no (direct) relationship to either the question or the answer. - aleksandr barakin
    • @alexanderbarakin, Thank you very much. I still have a question, but what if the targets targ0.axf and targ1.axf are going the same, but the dependencies are different? - Reffum
    • @Reffum, then it cannot be merged in this way. but, perhaps, the names of the targets partially coincide with the names of the dependencies (prerequisites), then you can try using the static pattern rules . - aleksandr barakin