How to cause the failure of the pipeline on a modern processor? There were a few ideas, but I'm not sure about them:

  1. In a conditional if statement, cram a bunch of conditions (for example, if (A & 0 & B & C .....), where A, B, C are any operations). I assumed that all operations will be loaded into the processor, but after the second one, the pipeline will be reset. Thus, it will be a simple size with about the number of conveyor steps.
  2. Using the GCC __builtin_expect extension, direct the processor to a false if-else branch. Assumed that the processor will be loaded operations that will not be performed. The conveyor will be reset.

Actually, the subject.

    1 answer 1

    Option 2 is appropriate. The transition prediction error is probably the only correct step. All other modern compilers are likely to optimize