in the continuation of the topic question about makefile

Tell me, what commands can you get so that object files are created not in a directory with makefiles, but in another directory?

let's say we do gcc -c hello.c and the object file hello.o appears in the directory with the makefile. how to make hello1.o appear in the hello1.o directory?

  • thanks ... it’s hard to read such a makefile from your example - xperious

3 answers 3

in view of the fact that this is absolutely not a “common practice”, “teams” it is impossible to get what you want, as far as I know. You will have to add the path you need in the makefile to the name of each file. An example of such a change .

and the compiler must also explicitly specify the path:

 $ gcc -o objects/hello.o -c hello.c

what should be roughly done:

  1. for convenience of manipulations, add (somewhere at the beginning of the file) a variable containing the path to the directory with the object files:

     dir = objects

  2. Mention of each object file to precede this variable. those.:

     cEci.o

    replaced by:

     $(dir)/cEci.o

    etc.

and for convenience, I would suggest a twice-listed enumeration of all object files also be transferred to a variable. instead:

 cEci.o cJulian.o ... main.o stdafx.o

write:

 $(objects)

then it will be easier to add the prefix "in one fell swoop" to all these names:

 objects_list = cEci.o cJulian.o ... main.o stdafx.o objects = $(addprefix $(dir)/,$(objects_list))

these two lines can also be placed somewhere at the beginning of the file.

     $ make VPATH=.. -C objects -f../Makefile

    This method allows you to change nothing in the Makefile, but it does not always work. The current directory is different, so if there are any include files with a path relative to it, sometimes it is necessary for the compiler to specify the path to search for them. For example, if the c-file is also an intermediate target, as with lex and yacc .

     $ CFLAGS=-I.. make VPATH=.. -C objects -f../Makefile

    In the Makefile itself, CFLAGS must be changed using += to preserve both assignments.

    All new files are created in objects, but if there are already object files in the current directory and they are newer than the sources, they will be used for linking. To ensure that target and intermediate target files are not searched by VPATH , you can use the vpath directive inside the Makefile to selectively expand the source search. I suggest the following preparation for the start of the Makefile:

     SRC := $(dir $(lastword $(MAKEFILE_LIST)))# каталог где находится этот Makefile (если до этой директивы не было include) # для компиляции из другого каталога (где будут временные файлы и результат) vpath %.c $(SRC) vpath %.h $(SRC) vpath Makefile $(SRC)

    Now you can compile with the command:

     make -C objects -f../Makefile

      A small example makefile for small projects. Here, all * .c files are collected in one project, and * .c files are also taken into account depending on * .h

       EXEC=gtk_test OBJ_CATALOG=.obj/ DEPEND_CATALOG=.depend/ SOURCE=$(wildcard *.c) OBJS=$(patsubst %.c,$(OBJ_CATALOG)%.o,$(SOURCE)) DEPEND=$(patsubst %.c,$(DEPEND_CATALOG)%.d,$(SOURCE)) CXX=gcc CFLAGS=-g2 -Wall -I. `pkg-config --cflags gtk+-3.0` LDFLAGS=-g2 LIB=`pkg-config --libs gtk+-3.0` $(EXEC):$(OBJS) $(CXX) $(LDFLAGS) -o $@ $^ $(LIB) $(OBJ_CATALOG)%.o:%.c $(CXX) $(CFLAGS) -c $< -o $@ $(DEPEND_CATALOG)%.d:%.c $(CXX) -MM -I. $< | sed -e '1s/^/.obj\//' > $@ include $(DEPEND) .PHONY:clean clean: -rm -f $(EXEC) *~ $(OBJ_CATALOG)*.o $(DEPEND_CATALOG)*.d