Consider the expansion of the x86-64 architecture, a four-level hierarchy of virtual memory pages.
With a TLB miss, you will need to conduct additional readings from memory (PLM4, PDP, PD).
The question is how to get PTE without unnecessary memory calls (or reduce them)? How to optimize the process? The question is theoretical.
Solved.
In TLB, in addition to direct translation of the virtual address to the physical address of the page, you can store pointers to the page tables.
Thus, we can immediately refer to PD and further to the physical page, if we don’t find the pointer to the required PD, we can turn to PDP and so on (from the least significant bits).
Source: https://ru.stackoverflow.com/questions/534786/
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