And specifically there is a question about pipelining in these architectures. I heard that in EPIC there is a “protected pipeline” (it will stop if we try to use the result of the instruction before it is ready) and it uses DPL (Deep Pipeline-Latency).
In the same VLIW "unprotected pipeline" and there are no interlocks. But, unfortunately, I can not find information anywhere on the Internet. And is this information correct? Can there be a detailed source (or you)? Thank!
UPD: I also heard that there are subclasses in VLIW architectures: recording the result of executing the instruction strictly after a certain number of cycles or earlier "maximum delay" - maybe this somehow makes a difference to the architecture ...
