Good day to all. A question. The error "ERROR: HDLCompiler: 806-Line 33: Syntax error near" entity "flies." The syntax is written correctly (sort of). Semantic component also seems to have. Tell me what to do please. Ps still very much tortured the error "design is empty". If anyone knows what to do with it, information would also be good. Thank.

entity massive is port ( clk : in std_logic; reset : in std_logic; sin : out std_logic_vector(15 downto 0)); end massive; architecture Behavioral of massive is type my_type is array (0 to 16) of signed (14 downto 0); signal x : my_type; signal y : my_type; signal z : my_type; signal j : my_type := ("001111111001000", "001101111100010", "001101101101010", "000110111101010", "000011011111100", "000001101111110", "000000110111111", "000000011100000", "000000001110000", "000000000111000", "000000000011100", "000000000001110", "000000000000110", "000000000000011", "000000001000010", "000000000000010", "000000000000001"); signal x1 : std_logic_vector(15 downto 0); signal y1 : std_logic_vector(15 downto 0); signal z1 : std_logic_vector(15 downto 0); begin process(clk, reset) begin if rising_edge(clk) then if reset <= '1' then for i in 0 to 15 loop if (z(i) >= '0') then x1(i) <= x(i+1) - (y(i+1)/2**i); y1(i) <= y(i+1) + (x(i+1)/2**i); z1(i) <= z(i) - j(i); else x1(i) <= x(i+1) + (y(i+1)/2**i); y1(i) <= y(i+1) - (x(i+1)/2**i); z1(i) <= z(i) + j(i); end if; sin <= y1; end loop; end if; end if; end process; end Behavioral;

    1 answer 1

    I did not see the listing of the used libraries in the listing of the presence. I expected to see the beginning in the following form:

     library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity massive is

    I would like to warn you in advance that if you use the designation "**" as a function of degree - I am afraid to upset you, everything is not so simple. And the cycles are also not easy. VHDL is a hardware description language and is completely different from programming languages. Judging by the code, you write CORDIC, am I right?