The system (miles, not mor) gets a positive integer X and translates a positive integer Y so that: Y=\floor{x/3} when floor is an integer part.

I need to write a program in Verilog using the finite state machine that I drew:

automatic circuit

The system has input reset and if reset==1 , then it will be output==0

Where do I begin?

    1 answer 1

    First describe your program, that is, specify the inputs and outputs, for example

     module my_project( input1, input2, output1 )

    where input1, input2, output1 are the ports of your block for which you receive data. Next, you need to describe each of the ports, for example:

     input input1; input [15:0] input2; output [3:0] output1; reg [3:0] output1;

    I note that I specified one of the ports as a register. After this, a direct description of the logic of your program begins. You need to determine whether you are going to implement a synchronous or asynchronous scheme. If you are not sure that you understand what I mean, it is best to read various literature on the subject of hardware description languages, for example, various books from Pong Chu or Harris and Harris Computer Architecture.