The primary task is to create a file in which, in the Verilog language, the correspondence of the value of samples for the DAC to the input values of the address bus is described. Python is used to generate the file. Below is the code:
import math A = 2**24 - 1 T = 1/(2**8) n = 0 file = open("D:\TDM\sin.txt","w") while n < 2**8: S = A * 0.7 / 2 * math.sin(2 * math.pi * T * n) + A / 2 file.write("if(addr = 8'd" + str(n) + ")" + "out_sample <= 24'd" + str(S) + "; \n") n += 1 file.close() The result is a file, a fragment of the contents of which is presented below in the Verilog format:
введите if(addr = 8'd0)out_sample <= 24'd8388607.5; if(addr = 8'd1)out_sample <= 24'd8532714.21355256; if(addr = 8'd2)out_sample <= 24'd8676734.122609375; if(addr = 8'd3)out_sample <= 24'd8820580.474962479; if(addr = 8'd4)out_sample <= 24'd8964166.622947972; if(addr = 8'd5)out_sample <= 24'd9107406.075639347; if(addr = 8'd6)out_sample <= 24'd9250212.550946364; if(addr = 8'd7)out_sample <= 24'd9392500.02758818; if(addr = 8'd8)out_sample <= 24'd9534182.796909336; if(addr = 8'd9)out_sample <= 24'd9675175.514507454; if(addr = 8'd10)out_sample <= 24'd9815393.251641508; The script works as needed, but the numbers are represented in decimal format. For greater readability of this code fragment, it is necessary to convert these numbers into hexadecimal. But in the case of using the command
hex() Suppose the number 1 will be 0x1. How to get the value without the prefix "0x" as well as convert them to a single display for 8-bit numbers?
That is, you need to get not 0x1, but 01, in order to form a number for Verilog format 8'h01.
"{:x}".format(n); read about the format () syntax - it will be much more comfortable for them to form the whole line ... - Fat-Zer