Help me figure out how to write a makefile to build a kernel module for Linux. I have such a Makefile :

 obj-m += hello.o all: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
  • What is obj-m for?
  • make -C goes to the directory. What is the build directory at the end of the path for?
  • M = $ (PWD) What does M relate to? Is this a command variable or key? Where is $ (PWD) defined and what is the value of this variable?
  • What are modules and clean at the end of the first and second command?

1 answer 1

I will answer briefly:

  1. obj-m is the make utility variable, the kernel build scripts invoked by the listed commands take from it the names of the modules (the names of the files with source codes) from which the kernel module will be assembled.

  2. This is an indication to the make utility of the current directory where to look for the Makefile, respectively, the build is the final build location.

  3. M is an environment variable that tells the kernel build scripts where your source codes are located and where to put the build result. By default, the result can be in the current directory.

  4. modules, clean - tragets are build targets, the make utility looks for all the listed targets in the current Makefile (in this case, in the folder specified with the -C option), and executes the build rules listed there.

To expand the knowledge, I recommend to google the rules for writing a Makefile, then much will become clearer.