In the ARM Thumb processors, instruction B makes it possible to switch only to a limited offset. Therefore, the IAR compiler generates additional code by transferring the execution from flash-memory to main memory, with which this restriction is bypassed, and this code is called Veneer. Here is an example disassembler:

 ;Veneer (6) for flashPageEraseInfo: LDR PC, [PC, #0x0] .word 0x200067c9 ;flashPageEraseInfo

Why does the LDR command have an offset of 0 rather than 4? After all, the address to which you want to go is in the next memory cell after the PC .

Another strange thing is that with step-by-step tracing, this code is executed, and the program goes to the correct address, and during normal execution HardFault occurs. Maybe you need to add a barrier here? But I do not know how to set up a compiler for this.

  • At the time of the execution of the instruction, the RS is already incremented and indicates the following word. About the rest I can not tell you anything .. - tum_
  • Adding the DSB and ISB barriers in the C-code before calling the flashPageEraseInfo function, that is, two instructions before the specified code fragment, I got rid of the problem. The problem disappears only with pairwise use of barriers and only in this order. - maestro

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